common-stop
triggered measurements, common-start, Time-to-Digital Converter (TDC), Coincidence Measurement
In picosecond time-interval analysis, a common-stop architecture refers to a measurement paradigm where the timing causality is effectively inverted: time intervals are recorded relative to a shared trigger signal (the "gate" or "stop") that arrives chronologically after the target measurement pulses. In this configuration, the pulses arriving on the individual input channels act as independent "starts", while the common trigger signal simultaneously terminates all ongoing measurements.
Working Principle: The "Look-Back" Approach Mathematically, a common-stop system calculates negative relative time differences ($\Delta t = t_{start} - t_{common_stop}$). Because the TDC cannot predict when (or if) a stop signal will arrive, the continuously incoming start events on the input channels must be temporarily buffered in the hardware's internal FIFOs. When the common-stop trigger finally arrives, it establishes the reference zero-point ($t_0$). The system then effectively "looks back" in time over a predefined temporal window and extracts all start events that were buffered during that specific interval.
Figure 1: The look-back approach. The common-stop trigger sets the absolute reference time (t₀), allowing the TDC to extract valid past start events from its internal hardware buffer.
Why Common-Stop? (Data Reduction and Noise Rejection) The primary advantage of a common-stop architecture is massive data reduction in experiments with highly asymmetric event rates. If random detection events (starts) occur at extremely high frequencies—due to high background noise or dark count rates—but the validating macro-event (stop) is rare, a common-start setup would overwhelm the data transfer bus (PCIe) with irrelevant data. Instead, the common-stop trigger acts as a highly efficient, asynchronous hardware filter: data packets are only generated and transmitted to the host CPU if the chaotic start events are successfully validated by a subsequent stop trigger.
Figure 2: In delayed coincidence setups, complex logic generates a delayed common-stop signal, validating only the relevant particle events that were temporarily stored in the TDC's buffer.
Key Applications Common-stop configurations are essential whenever rare but causally linked events must be isolated from dense background noise. Prominent applications include:
- High-energy and theoretical nuclear physics (e.g., detecting decay cascades or cosmic muons).
- Delayed coincidence measurements.
- Particle physics detectors with complex trigger logic, where the validation of an event takes computational time in the front-end electronics, causing the final validation trigger to arrive at the TDC with a significant delay.