bin size, jitter and RMS

The bin size, jitter, and RMS measurement error are all important parameters that play a role in the digital acquisition of time data.

• The bin size refers to the width of the time windows into which the data is divided during the measurement. The smaller the bin size, the higher the temporal resolution of the measurement. However, if the bin size is too large, there may be an overlap of data between each time window, resulting in an inaccurate measurement.
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• Jitter refers to the deviation in the time it takes for data to arrive at each time window. When jitter is high, data in a circuit can be erratic or inconsistent, resulting in an inaccurate measurement. Jitter is not directly related to bin size and therefore cannot be calculated directly from it. Jitter can be considered as the measure of the temporal variability of the acquired signal edges. There are TDCs on the market that offer good time resolution but have high jitter, so that the high time resolution initially impresses but is of no practical use. cronologic TDCs, on the other hand, have such a significantly low jitter that it can be safely ignored in relation to the bin size.
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• The RMS measurement error refers to the average deviation between the actual values of the input data and the values generated by the measurement. The lower the RMS measurement error, the more accurate the measurement.

Please note: Our high-end TDCs, such as xHPTDC8 and xTDC4 are realized using dedicated ASICs that ensure a controlled and highly uniform bin size. Consequently, residual jitter contributions are substantially smaller than the inherent quantization error. For short time intervals, the measurement uncertainty is therefore predominantly governed by the bin size. Under these conditions, the maximum error approaches approximately half a bin, the root mean square (RMS) error amounts to about 0.8 bins, and the full width at half maximum (FWHM) corresponds to roughly 2 bins.

On the other hand there are TDCs on the market that, unlike chronologic TDCs, are based on an FPGA-implemented carry chain design and therefore have a much higher jitter that is significantly above the digital resolution. In this case, the time jitter is the limiting factor for the usable resolution of the TDC.