bin size

The bin size is the width of the discrete time intervals used by a time-to-digital converter (TDC) to quantize measured time intervals. It defines the smallest time increment that can be represented digitally.

In time-to-digital converters, the bin size is the quantization unit for time measurements and therefore defines the digital resolution of the TDC. However, this value alone is not sufficient to assess the practically achievable timing resolution. In particular, timing jitter plays a crucial role.

Our high-end TDCs, such as xHPTDC8 and xTDC4 are implemented using dedicated ASICs that ensure a highly controlled and exceptionally uniform bin size. As a result, the residual jitter contributions are significantly smaller than the inherent quantization error. For short time intervals, the measurement uncertainty is therefore dominated by the bin size. Under these conditions, the maximum error approaches approximately half a bin, the root mean square (RMS) timing uncertainty is about 0.8 bins, and the full width at half maximum (FWHM) is approximately 2 bins.

In contrast, there are TDC architectures whose timing jitter exceeds their nominal bin size. In such systems, simply reducing the bin size does not improve the effective timing resolution, because the measurement uncertainty is dominated by jitter rather than quantization. Unlike cronologic TDCs, these systems are typically based on FPGA-implemented carry-chain architectures.

The bin size should therefore never be considered in isolation as a measure of a TDC's performance. Parameters such as timing jitter, differential non-linearity (DNL), and integral non-linearity (INL) are equally important for determining the actual timing accuracy.

Further information on this topic can be found in this application note.

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