cycle-to-cycle jitter

Cycle-to-cycle jitter is a measure of the deviation between two consecutive clock periods and is therefore calculated as the time difference between random periods of adjacent cycles.

For many TDC products on the market, this inaccuracy is a major cause of measurement errors. However, with cronologic products, the cycle-to-cycle jitter is significantly lower than the bin size.

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Our high-end TDCs, such as xHPTDC8 and xTDC4 are realized using dedicated ASICs that ensure a controlled and highly uniform bin size. Consequently, residual jitter contributions are substantially smaller than the inherent quantization error. For short time intervals, the measurement uncertainty is therefore predominantly governed by the bin size. Under these conditions, the maximum error approaches approximately half a bin, the root mean square (RMS) error amounts to about 0.8 bins, and the full width at half maximum (FWHM) corresponds to roughly 2 bins. 

On the other hand there are TDCs on the market that, unlike chronologic TDCs, are based on an FPGA-implemented carry chain design and therefore have a much higher jitter that is significantly above the digital resolution. In this case, the time jitter is the limiting factor for the usable resolution of the TDC.

Caution should always be exercised when comparing jitter specifications, as different characteristics of the clock cycle distribution may be specified. Common specifications are the 1-sigma interval or the 95% interval of the distribution.