cycle-to-cycle jitter

see also:

short-term jitter, Aperture Jitter, Abtasttakt (Sampling Clock), SNR (Signal-to-Noise Ratio), ENOB, Quantisierungsfehler, Bin-Size, TDC, Time Tagger, ADC, TCSPC, ToF-MS

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Cycle-to-cycle jitter (also referred to as C2C jitter or short-term jitter) measures the instantaneous variation in duration between two consecutive clock cycles. It is mathematically defined as the difference between adjacent clock periods:

Jcc(n) = Tₙ₊₁ − Tₙ

C2C jitter is evaluated statistically across a large sequence of clock cycles and expressed either as a root-mean-square value (RMS, Jcc,RMS) or as a peak-to-peak value (Jcc,pk-pk). Differencing directly adjacent clock periods suppresses low-frequency variations such as drift and wander (similar to a high-pass filter), making C2C jitter a key metric for high-frequency phase noise in oscillators, clock distribution trees, and phase-locked loops (PLLs).

Relevance for High-Speed Data Acquisition (ADCs & TDCs)

In high-speed data acquisition systems, clock stability is crucial for preserving signal integrity and timestamp fidelity across gigahertz domains:

  1. Impact on High-Speed Analog-to-Digital Converters (ADCs / Digitizers)
  • Sampling Voltage Error: When digitizing fast analog signals with steep slew rates (large dV/dt), sample clock jitter translates directly into amplitude uncertainty:
    ΔV ≈ (dV/dt) · Δt
  • SNR and ENOB Degradation: At high analog input frequencies (fin), the achievable signal-to-noise ratio is primarily limited by clock and aperture jitter (tj):
    SNRjitter = −20 · log₁₀(2π · f_in · tj,RMS)
    cronologic designs its high-speed digitizers in its Ndigo series with minimal C2C jitter. Minimizing jitter contributes to the digitizers' excellent signal-to-noise ratio, ensuring an optimal effective number of bits (ENOB) and accurate peak-heights measurements for fast transient events, occurring, for example, in TOF-MS, LIDAR, or quantum readout.
  1. Role in high-precision time measurement with Time-to-Digital converters (time taggers)
  • Coarse Counter & Interpolator Fidelity: TDCs pair a coarse clock counter with fine delay-line interpolation. Reference clock C2C jitter creates phase boundary ambiguity between cycles, leading to timing uncertainty and artificial peak broadening in measurement histograms.
  • Quantization-Limited Performance: cronologic's ASIC-based TDCs (such as the xHPTDC8 and xTDC4) deliver highly uniform bin sizes with negligible differential nonlinearity (DNL). Because internal circuit and clock jitter are engineered to remain significantly below the bin size, measurement uncertainty of time intervals is strictly quantization-limited, unlike in FPGA carry-chain TDCs where jitter often dominates the effective resolution.

For detailed experimental tests and histograms, refer to our application note on Quantization vs. Jitter in TDCs.

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Schematic representation of consecutive clock cycles with different period durations Tₙ and Tₙ₊₁. Their difference represents cycle-to-cycle jitter.

The graphic illustrates cycle-to-cycle jitter using consecutive clock periods. Due to short-term timing fluctuations, their durations Tₙ and Tₙ₊₁ may differ. Cycle-to-cycle jitter is defined as the difference between these periods: Jcc(n) = Tₙ₊₁ − Tₙ. The larger this difference, the more the clock timing varies from one cycle to the next, potentially affecting sampling accuracy in high-speed ADCs and timing precision in TDCs.

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