The Ndigo6G-12 will use Partial Reconfiguration to improve performance, power consumption, and value for money for our customers.
Partial Reconfiguration is a technique where the FPGA of the device does not implement all features simultaneously. Instead, only the functionality currently requested by the users is loaded so that this results in a dynamic exchange of functions.
Our cofounder Kolja Sulimma has been involved in the research of partial reconfiguration since the 1990ies at UC Berkeley with Prof. Dave Patterson, TU Kaiserslautern, University of Frankfurt and CERN. But this is the first time he is using the approach in a commercial product.
In the Ndigo series, the different operation modes with or without interleaving require very different datapath structures. In the Ndigo5G-10 this is achieved by many multiplexers and thousands of wires. The Ndigo6G-12 will instead have five different datapaths and only one of them will be loaded at a time. Each of the datapaths is much smaller and simpler than a combined datapath would be. This frees up resources for additional features such as allpath filters to align data to the trigger phase or dynamic offset calibration to improve SFDR.
The approach also makes it easy to implement other functionalities in the devices in the near future such as hardware averaging or a spectrum analyzer.